Project 2 of the triptych

Fog-Crypto Core

A HW/SW co-design module dedicated to offloading critical computations and securing IoT nodes. Positioning: data integrity at the source for sensitive industrial infrastructures.

Phase: framing — structure initialized

Project card

Developed by — Helveticore OÜ (Estonia)
Maturity — CMMI Level 3 “Defined”
Discipline — HW/SW co-design, SystemVerilog / Verilog
Host buses — SPI / PCIe (high-speed)

Sub-projects (src/)

rtl/ — logic blocks optimized for FPGA.
bus-interfaces/ — low-level SPI / PCIe communication to the embedded Linux host.
crypto-engines/ — hardware encryption and real-time signal pre-processing.
host-integration/ — drivers and interface on the host processor side.

Milestones & risks

Milestones

1 · Virtual test bench: RTL co-simulation + software reference model.
2 · Basic logic blocks + simulated SPI/PCIe interface.
3 · Line-rate encryption engine validated in simulation.
4 · Integration on an embedded Linux host board (real benchmark).

Key risks (RSK)

Meeting FPGA timing at target frequency — mitigated by RTL testbench and constraints.
HW/SW coherence of the SPI/PCIe interface — mitigated by a common interface contract.
Key security and side channels — to be addressed from design stage.

Current state: the project's CMMI structure is initialized (requirements, design, test bench, performance) and the project charter is set. Detailed artifacts remain to be written.